1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device having multiple global I/O line pairs.
2. Description of the Background Art
In semiconductor memory devices such as dynamic random access memories (DRAMs), simultaneous input/output of data of multiple bits has been required because of increase in number of banks as well as increase in transfer rate and capacity. However, conventional memory cell array structures cannot satisfy these requirements without difficulty.
A first cause of the above is increase in number of banks. Generally, DRAMs have employed bank structures for hiding disadvantages caused by low access. For example, an SDRAM employs 4 banks, an RDRAM employs 16 banks, and SLDRAM employs 8 banks. These DRAMs operate as if a plurality of independent memories are present in one chip. Although there is a tendency to increase the number of banks, this results in decrease in number of physical memory cells allocated to each bank so that it is difficult to ensure a wide bit width.
A second cause is that the number of data to be prefetched has been increased for achieving a high transfer rate. The above three kinds of DRAMs have already employed a so-called double data rate (DDR) technique in which input/output of data is performed using both rising and falling edges of a clock for increasing the data transfer rate. At present, it is impossible to achieve revolutionary increase in read/write speed. In view of this as well as the fact that an array operation speed may be reduced due to lowering of operation voltage, reduction in size of components, and increase in capacity and therefore array mat size, a prefetch method has become the mainstream rather than the DDR technique. In the prefetch method, data is fully fetched at a time from an array to a latch circuit or a register, and thereafter will be output gradually or little by little. For ensuring the quantity of data which can be prefetched, it is necessary to ensure a sufficient bit width with respect to the array mat.
A third cause is restrictions on the chip size. Although developed process techniques have reduced sizes of design tools, there is a tendency to increase the chip sizes in accordance with increase in capacity of the DRAMs. For minimizing the chip sizes within an allowed range, it has been attempted to increase division units of bit lines and word lines, and thereby to reduce the number of circuits other than the memory cell arrays. However, this increases the size of the sub-block, and therefore decreases regions where global I/O line pairs can extend. Even if the memory mat increases in size and the sense amplifiers which can be activated at a time increases in number, the number of bits cannot be increased because the number of global I/O line pairs for sending data from the memory cell arrays is restricted.
As an easy manner for ensuring a sufficient bit width, it can be envisaged to allow increase in number of interconnections by increasing a layout area of regions such as sense amplifier region, which are used for local I/O line pairs sending the data from the array mats, and sub-word driver regions or word line shunt regions, which are used for the global I/O line pairs. However, this manner results in increase in chip size.
For overcoming the above problems, such a semiconductor memory device has been proposed that local I/O line pairs are divided into a plurality of groups or sets, and the global I/O line pairs are arranged for divided groups of the local I/O line pairs in a one-to-one relationship, respectively (see U.S. Pat. No. 5,781,495).
In FIG. 2 of the above publication, a large number of global I/O line pairs extend not on word line shunt regions but on memory cell arrays. A plurality of local I/O line pairs are connected to each global I/O line pair. Only one bit line pair is connected to each local I/O line pair. Therefore, the local I/O line pair is directly connected to the global I/O line pair without interposing a switching element therebetween.
In FIG. 5 of the above publication, a large number of global I/O line pairs extend not on the word line shunt regions but on the memory cell arrays. Local I/O line pairs, which correspond to the global I/O line pairs in one-to-one relationship, respectively, are arranged across the global I/O line pairs.
In the semiconductor memory device shown in FIG. 2 of the above publication, only one bit line pair is connected to each local I/O line pair, and only one global I/O line pair is arranged for a plurality of bit line pairs arranged in each column. Therefore, the global I/O line pairs are excessively large in number. Further, this device must employ the global I/O line pairs which correspond to column select lines in a one-to-one relationship, respectively, so that excessively large parasitic capacities occur between these lines, resulting in disadvantageous decrease in operation speed and increase in power consumption.
In the semiconductor memory device shown in FIG. 5 of the above publication, the global I/O line pairs are always equal in number to the local I/O line pairs. Therefore, the number of the global I/O line pairs must be increased for increasing the number of local I/O line pairs, and consequently it is also necessary to increase the number of preamplifiers connected to the global I/O line pairs. Accordingly, this device suffers from the problem that increase in number of the local I/O line pairs causes extreme increase in layout area.